1. Field of the Invention
The present invention generally relates to relay boards provided in semiconductor devices, semiconductor devices, and manufacturing methods of semiconductor devices, and more specifically, to a relay board used for wiring the semiconductor chips to each other, or the semiconductor chip to and a wiring board or a lead frame, a semiconductor device having the relay board, and a manufacturing method of the semiconductor device.
2. Description of the Related Art
A chip stack type (stacked package) semiconductor device having a structure where semiconductor chips (semiconductor elements) of different functions are stacked on a die pad of a lead frame or a wiring board, and electrode pads of the semiconductor chips and a bonding pad on the wiring board or an inner lead of the lead frame or the electrode pads of the semiconductor chips are wired by bonding wires, is known.
In such a semiconductor device, depending on arrangements of electrode pads of the semiconductor chip and bonding pads of the wiring substrate or a bonding lead of the lead frame, or arrangements of plural stacked semiconductor devices, crossing or superposing of the bonding wires happens, the length of the bonding wire is too long, or the like so that wire-bonding may be hard to accomplish.
In order to solve such a problem, a relay board having a wire and a terminal formed on an end part of the wire has been suggested. More specifically, a structure where the semiconductor chip and the wiring board or the inner lead of the lead frame, or the electrode pads of the semiconductor chips are electrically connected by wire bonding via the relay board has been suggested.
For example, a structure where a wiring sheet having a wiring pattern and a terminal formed at an end part of the wiring pattern is provided between plural semiconductor chips is discussed in Japanese Laid-Open Patent Application Publication No. 2001-7278. A structure where a wiring layer for relay-wiring a wire for wire bonding is provided between plural semiconductor chips stacked on a board is discussed in Japanese Laid-Open Patent Application Publication No. 2002-76250. A structure where a rearranging sheet having an insulation sheet and plural conductive metal patterns formed on the insulation sheet is provided between plural semiconductor chips stacked on a board is discussed in Japanese Laid-Open Patent Application Publication No. 2002-261234. A structure where an interposer having a connection wire is provided between plural semiconductor chips stacked on a board is discussed in Japanese Laid-Open Patent Application Publication No. 2004-235352.
However, while sizes of the semiconductor chip and the wiring board and the number and the arrangement of the bonding pads formed on the wiring board or the electrode pads formed on the semiconductor chip are varied, designated wiring patterns and terminals are formed in the relay board in the related art discussed in the above-mentioned publications.
Accordingly, even if a terminal chip is proper for the design of a certain semiconductor device, the terminal chip may not always be proper for the design of other semiconductor devices. In other words, for every semiconductor device, the wiring pattern and the terminal are formed on the relay board as corresponding to the arrangement of the electrode of the semiconductor chip and the arrangement of the bonding pad of the wiring board or the lead frame.
Therefore, depending on the positional relationship between the semiconductor chip and the lead frame or the pad of the wiring board, the related art relay boards may not be used and therefore the relay boards have to be redesigned and remanufactured. Thus, the related art relay board may not be widely used.
The way of mounting a semiconductor chip on a semiconductor device, the arrangement of electrode pads of a semiconductor chip, or the connection structure between a semiconductor chip and a wiring board or a lead frame may need to be changed. In addition, for the purpose of improvement of yield in manufacturing existing semiconductor devices, positions of the bonding pads of the relay boards may need to be changed. The related art relay boards do not correspond to these structures and it is necessary to provide a relay board having a different structure.
Furthermore, the wiring patters of the related art relay boards are formed by using a photolithography technique. Hence, in the related art, a manufacturing cost for manufacturing the relay board and the semiconductor device having the relay board is high.
In addition, when the relay board is provided between the semiconductor chips, it is necessary to provide the relay board between the semiconductor chips at high precision so that the terminal of the relay board and the electrode pad of the semiconductor chip are positioned at designated corresponding positions.
For example, in a case where the relay board is provided between the semiconductor chips by using an apparatus having a positioning mechanism using image recognition, it is necessary to perform an operation for recognition of an arrangement and positioning of the relay board every time a single relay board is provided between the semiconductor chip. Such an operation requires a lot of time, as a result the productivity of manufacturing the semiconductor device is reduced so that the manufacturing cost for the semiconductor device is increased.